FIG. 1 illustrates a commonly-used six-transistor SRAM cell. A first inverter, comprising a P-channel transistor T.sub.1 and an N-channel transistor T.sub.2, and a second inverter, comprising a P-channel transistor T.sub.3 and an N-channel transistor T.sub.4, are interconnected in the familiar fashion to form a latch. An N-channel select transistor T.sub.5 couples the latch to a first bit line BL and an N-channel select transistor T.sub.6 couples the latch to a second bit line BL*. (The convention used throughout this document is that a signal or line marked with an "*" is, in normal operation, the logical complement of the signal or line having the same mnemonic, but lacking the "*".) The gates of T.sub.5 and T.sub.6 are coupled to a word line WL.
As is disclosed in U.S. Pat. No. 4,004,222, it is well known that testing SRAM cells by writing predetermined data to them and reading them after a waiting period is problematical. For various reasons, either the waiting period must be relatively long or some other measures, such as increasing the temperature, must be taken in order to increase the likelihood that defective cells will be identified by the test procedure. Any test techniques which require long waiting periods, high temperatures or other similar measures are unreasonably expensive.
Both U.S. Pat. No. 4,554,664 and U.S. Pat. No. 3,812,388 are directed to the design of latch circuits which might be useful in SRAM devices and which are said to be more easily testable than other such circuits. Neither, however, mentions either the problem of testing the data retention capability of such latch circuits nor a possible solution to the problem.
U.S. Pat. No. 4,680,762 is directed to the problem of testing semiconductor memory devices and is specifically directed to the problem of detecting "soft" cells in a dynamic RAM, or DRAM array. The disclosed method involves the application of a non-standard, time varying test signal to the word lines of the array and relies on the fact that certain "soft" DRAM cells reveal themselves by changing state under such conditions. The disclosed method and apparatus are not directed to the problem of testing SRAMs, dealing instead with DRAMs.
U.S. Pat. No. 4,685,086 is directed to the problem of detecting certain short-circuit type defects in SRAMs. In addition, a leakage current test is used. However, no method of detecting open-circuit type, or soft defects, is disclosed.